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A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller Clock-to-Q Delay Compared to the StrongARM & 6.3dB Lower Noise Compared to Double-Tail

https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830355

Lin, X. ; Megahed, M. ; Anand, T. ( June 2022 , International Symposium on VLSI Technology Systems and Application)

A single-clock-phase sense amplifier architecture with a strong regeneration is proposed. Designed in 22nm FinFET, the proposed architecture has a 9x smaller t CQ delay compared to the conventional StrongARM latch and 6.3dB lower input referred noise compared to the Double-Tail architecture for similar input transistor size and power consumption.
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A 27 Gb/s 5.39 pJ/bit 8-ary Modulated Wireline Transceiver Using Pulse Width and Amplitude Modulation Achieving 9.5 dB SNR Improvement over PAM-8

https://doi.org/https://doi.org/10.23919/VLSICircuits52068.2021.9492426

Megahed, M ; Chun, Y ; Wang, Z ; and Anand, T ( June 2021 , Symposium on VLSI Circuits)

This paper presents a novel 8-ary modulation technique with higher SNR compared to the PAM-8. The proposed modulation (SNR-Enhanced), modulates the pulse width and amplitude to achieve an average SNR improvement of 9.5 dB over PAM-8 in the near-end eye at the cost of 8.2% reduction in the horizontal eye margin. Using 3-tap FFE and CTLE, the proposed transceiver achieves 1×10 -7 BER at 9 dB channel loss with an efficiency of 5.39 pJ/bit in the 65 nm CMOS process.
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